Tydi Tools: Open-Source EDA Toolchain for Fast HW Debugging of Chisel High-Level HDL

This hands-on tutorial introduces participants to the Tydi ecosystem, an open-source hardware design and debugging framework for high-level hardware development in Chisel and other HLS languages such as SpinalHDL and Clash. The tutorial focuses on improving hardware design productivity, traceability, and debugging by preserving high-level type and behavioral information throughout the hardware design flow. Participants will explore how modern open-source Electronic Design Automation (EDA) tools can be used to move from high-level hardware descriptions to synthesizable RTL, using advanced debugging workflows.

The tutorial is divided into two complementary parts. In the first part, attendees will begin with a Chisel hardware design and use Tydi and Tydi-Chisel to generate type-aware intermediate representations and synthesizable Verilog. This section demonstrates how high-level type information can be preserved across the design stack and how this information improves analysis, verification, and maintainability compared to traditional RTL-centric methodologies.

The second part of the tutorial focuses on debugging complex hardware systems using Tywaves and ChiselTrace. Participants will work with a Chisel design containing an intentionally inserted bug and learn how to trace faulty behavior from waveform activity back to the original Chisel source code. Using type-aware waveforms and behavioral signal dependency graphs, attendees will gain practical experience with advanced debugging techniques that significantly reduce the effort required to identify and resolve hardware design issues.

Preparation for the tutorial

Participants are encouraged to download the Tydi tools Docker image before the tutorial, which contains the tools used during the hands-on sessions. Please follow the instructions here: hdltypetech/tydi-tools.

Target audience and expertise level

The tutorial is intended for students, researchers, hardware engineers, and practitioners interested in modern hardware design methodologies, hardware debugging, FPGA/ASIC development, and open-source EDA tools. Familiarity with digital design concepts and basic hardware description languages is recommended. Prior experience with Chisel is helpful but not strictly required, as the tutorial includes introductory guidance on the Tydi toolchain and workflow.

What participants will learn

Following this tutorial, participants will be able to:

1. Use the Tydi ecosystem for high-level hardware design in Chisel
2. Use type-aware intermediate representations to improve hardware traceability and debugging
3. Debug Chisel hardware designs using Tywaves and ChiselTrace
4. Use behavioral dependency tracing and type-conserving waveforms with ChiselTrace to simplify fault localization
5. Use open-source EDA tooling to support both research and industrial hardware development workflows

Related publications

• C. Cromjongh et al., "Hardware-Accelerator Design by Composition: Dataflow Component Interfaces With Tydi-Chisel," IEEE Transactions on VLSI Systems, vol. 32, no. 12, pp. 2281–2292, 2024.
• R. Meloni et al., "Tywaves: a typed waveform viewer for Chisel," IEEE Nordic Circuits and Systems Conference, 2024.
• J. Brand et al., "ChiselTrace: Typed Behavioral Debugging in Chisel Through Signal Dependency Tracing," IEEE Nordic Circuits and Systems Conference, 2025.

Tutorial presenters

Casper Cromjongh, TU Delft
Zaid Al-Ars, HDL TypeTech

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