HEART 2026 – International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies

HEART 2026 Program

Day 1 — June 17

Time	Session	Details
08:30–09:00	Registration	Registration
09:00–09:05	Welcome	Welcome Session
09:05–10:00	Keynote	The Need for Highly Efficient Accelerators in the Age of Agentic AI Speaker: Tobias Becker
10:00–10:15	Coffee Break
10:15–10:55	Invited Talk	BrainScaleS - Brain-inspired neuromorphic processors from Heidelberg Speaker: Johannes Schemmel
10:55–11:10	Coffee Break
	Machine Learning & Neural Network Acceleration I	Session Chair: Jason Anderson
11:10–11:30	Machine Learning & Neural Network Acceleration I	ARES: Dataflow Co-Design for Embedded Swin Transformer Acceleration on SoC-FPGAs Authors: João Rodrigues, Horacio Neto and Mário Véstias.
11:30–11:50	Machine Learning & Neural Network Acceleration I	SmartFuse-LLM: Fusing Computation into Collectives for Efficient Tensor-Parallel LLM Systems Authors: Xiteng Yao, Bangjie Xue, Anthony Skjellum and Martin Herbordt.
11:50–11:52	Poster Pitch	Poster Pitch Intro
11:52–11:53	Short and WIP papers	Lightweight Adjacency Estimation for Irregular Object Reassembly using Siamese Networks Authors: Kokoro Kodama, Keisuke Sugiura, Takuya Kojima and Yoshiki Yamaguchi.
11:53–11:54	Short and WIP papers	Quantized NN Workflow for Low-Latency Multi-Qubit State Discrimination on FPGA Authors: Pradeep Kumar Gautam, Shantharam Kalipatnapu, Shankaranarayanan H, Ujjawal Singhal, Benjamin Lienhard, Vibhor Singh and Chetan Singh Thakur.
11:54–11:55	Short and WIP papers	An FPGA-based Ethernet Interconnect for Quantum Error Correction Authors: Mizuki Sakata, Yoshito Higa and Yasunori Osana.
11:55–11:56	Short and WIP papers	An Evaluation of RRT* Algorithm with Relaxed Data-Dependency for Pipelined Accelerators Authors: Koh Tomita, Tomonori Izumi and Yoshiki Yamaguchi.
11:56–11:57	Short and WIP papers	Real-Time Hyperspectral Imaging System for Surgical Guidance Authors: Dismas Ezechukwu and Dinesh Bhatia.
11:57–11:58	Short and WIP papers	TinyRVV: A Minimalist’s Vector Subset for RISC-V Authors: Jerry Yun and Guy Lemieux.
11:58–11:59	Short and WIP papers	Procedural Surface Rendering on a BRISKI-Based FPGA Many-Core Architecture: A Case Study Authors: Kevin Klein, Riadh Ben Abdelhamid and Dirk Koch.
11:59–12:00	Short and WIP papers	FDBench: A Paired Golden-Buggy Benchmark for FPGA Debugging Authors: Yanjun Lu, Lester Kalms, Narasingh Prasad Joshi and Diana Goehringer.
12:00–13:30	Lunch
13:30–14:00	Posters	Poster Session
	Quantum Computing	Session Chair: Yoshiki Yamaguchi
14:00–14:20	Quantum Computing	ESSPER2: Research-Oriented FPGA Cluster for Quantum Error Correction and HPC Applications Authors: Kentaro Sano, Tomohiro Ueno, Fuga Kato, Kazuya Mochizuki, Katsuhiko Ota and Nozomu Matsunaga.
14:20–14:40	Quantum Computing	From XLS to SFQ: Automated Topology-Constrained Pipeline Synthesis for Single-Flux-Quantum Circuit Design Authors: Hikaru Kobayashi, Mebuki Oishi and Shinya Takamaeda-Yamazaki.
14:40–15:10	Coffee Break and Posters
	Cryptography and Security	Session Chair: Kentaro Sano
15:10–15:30	Cryptography and Security	High-Throughput FPGA Acceleration of the Number Theoretic Transform for FV Homomorphic Encryption Authors: Benjamin Steeg, Zahra Mojtahedin, Hassan Nassar and Joerg Henkel.
15:30–15:50	Cryptography and Security	KHONSU: Kernel Hash Offload Network of Swappable Units for Post-Quantum Signatures Authors: Mohamed El-Hadedy and Wen-Mei Hwu.
15:50–16:20	Coffee Break and Posters
	Numerical / Arithmetic Hardware	Session Chair: Ryohei Kobayashi
16:20–16:40	Numerical / Arithmetic Hardware	Systematic Function Approximation on FPGAs to Address Accuracy and Throughput Issues in oneAPI and Vitis HLS Math Libraries Authors: Gerrit Pape, Christian Plessl and Tobias Kenter.
16:40–17:00	Numerical / Arithmetic Hardware	Hardware Sharing for Area Optimization of Floating-Point ALUs Authors: Rikuto Ide, Tanvir Ahmed, Boma Adhi, Shunya Kawai, Omkar Bhilare and Jason Anderson.
18:15-	Social Event	Banquet (Kultur Brauerei)

Day 2 — June 18

Time	Session	Details
09:00–09:30	Registration	Registration
09:30–10:30	Keynote	From Prototype to Planet-Scale: A Decade of Acceleration at Hyperscale Speaker: Andrew Putnam
10:30–11:00	Coffee Break
	HLS and Domain-Specific Applications	Session Chair: Frank Hannig
11:00–11:20	HLS and Domain-Specific Applications	Expanding and partitioning HLS-compatible software regions for CPU-FPGA systems via code transformations Authors: Tiago Santos, João Bispo and João Cardoso.
11:20–11:40	HLS and Domain-Specific Applications	Exploring the AMD Versal System-on-Chip for Protein-based Phylogenetics Authors: Nils Rutgers and Nikolaos Alachiotis.
11:40–12:00	HLS and Domain-Specific Applications	Ray Marching on FPGAs Authors: Kevin Klein and Dirk Koch.
12:00–13:30	Lunch and Posters
	RISC-V & Multi-Processor Architectures	Session Chair: Riadh Ben Abdelhamid
13:30–13:50	RISC-V & Multi-Processor Architectures	SYNtzulu-Conv: Enabling Spiking 2D Convolutions for Sensor Data Analysis on Low-Power FPGAs Authors: Gianluca Leone, Federico Mura, Luigi Raffo and Paolo Meloni.
13:50–14:10	RISC-V & Multi-Processor Architectures	High Performance Multi-Processor Systems on FPGA Authors: Martin Langhammer and Bogdan Pasca.
14:10–14:30	RISC-V & Multi-Processor Architectures	MXM-RVV: Multicore and Multithreaded RISC-V Vectors Authors: Joseph Maheshe and Guy Lemieux.
14:30–15:10	Coffee Break and Posters
	Machine Learning & Neural Network Acceleration II	Session Chair: Mirjana Stojilovic
15:10–15:30	Machine Learning & Neural Network Acceleration II	A Reconfigurable Multi-Kernel FPGA Accelerator for Kernel Ridge Regression Authors: Yousef Alnaser, Wei-Jie Ng, Jan Langer and Harald Kuhn.
15:30–15:50	Machine Learning & Neural Network Acceleration II	Unsupervised Anomaly Detection for Event Cameras with Lightweight Spatio-Temporal Encoder on FPGA Authors: Hui Yang, Keisuke Sugiura, Takuya Kojima and Yoshiki Yamaguchi.
17:00-	Social Event	Castle Visit, City Tour and Dinner

Day 3 — June 19

Time	Session	Details
08:30–09:00	Registration	Registration
09:05–10:00	Keynote	FPGAs in High-Performance Computing: Challenges and Opportunities Speaker: Tobias Kenter
10:00–10:10	Coffee Break
10:10–13:00	Tutorials	Tutorials — SNN
13:00–14:10	Lunch
14:10–17:00	Tutorials	Tutorials — OpenSource EDA
17:00	Social Event	HEART Farewell BBQ

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